Nonvolatile memories, known as flash memory devices, have become very popular in a variety of uses including mobile phones, digital answering machines, and personal digital voice recorders. Low pin count, low cost, and ease-of-use are key factors for the wide utilization of flash memory.
Contents of a sequential type of flash memory may be accessed by supplying an initial address and applying a number of clock cycles equal to the number of sequential addresses desired for access in a memory operation. An internal address counter automatically increments an access address with each clock. Data from sequential addresses are available with each successive clock cycle. This avoids any requirement of additional address sequencing externally. This capability allows sequential reading to cross page and sector boundaries seamlessly.
To conduct a continuous read operation in a nonvolatile memory device, a read command is given which includes a starting memory address. After allowing a period of time for internal read operations and address decoding, a first byte of data is available from the initial address given. If a redundant bit or bits are required, the read operation must incorporate any redundant memory bits used into a final data word before the data are output.
A drawback of reading continuously from prior sequential memories involving redundancy has been the amount of latency after a read command is entered until data are output. Access time is increased to accommodate reading redundant bits in addition to the bits of the original location. This is especially true when the number and cost of reading circuits is kept the same as a part without redundancy. The delay from read command input to data output degrades an efficiency of continuous read operations.
With reference to FIG. 1, a prior art nonvolatile memory 100 contains a memory array 105 including a plurality of bit memory blocks 115 organized in parallel to form data words. The memory array 105 also contains redundant bit memory blocks 117 that are incorporated when a faulty bit is detected.
An output of each bit memory block 115 connects to a corresponding position of a multiplexed register 122. Each bit memory block 115 is associated with two redundant bit memory blocks 117. Each redundant bit memory block 117 has an output connected to a corresponding location of the multiplexed register 122 at one of two additional positions per location. Each output of the multiplexed register 122 connects to an input of a sense amp register 120. Each output of the sense amp register 120 connects to a corresponding input location of a memory register 127. Outputs of the memory register 127 connect to a multiplexer (MUX) 133.
A clock generator 155 receives a clock signal from a serial clock (SCK) input 160. A serial data input (SI) 145 of the nonvolatile memory 100 connects to a controller 140. Commands, addresses, and data are received through the serial data input 145. The controller 140 provides control input to the clock generator 155, the multiplexed register 122, the sense amp register 120, the memory register 127, and an address decoder 150.
Three output lines of the clock generator 155 connect clocking signals, which are encoded to select one of eight possible values. A selection of the inputs to the multiplexer 133 is sequenced through under control of the signal values on the three clock output lines. An output of the multiplexer 133 connects to a serial output (SO) 135.
The controller 140 receives a continuous read command followed by three bytes of address information. The first two address bytes received determine a data byte location to the sector, block, and page level. After decoding the continuous read command, the controller 140 and address decoder 150 determine an initial memory location and connect the appropriate bit memory locations of the memory array 105 to the multiplexed register 122.
Locations requiring replacement of their contents by redundant memory 117 have been previously determined. With the initial memory location determined, the controller 140 compares the single memory location addressed with the previously determined locations requiring replacement of contents. A determination of a requirement for replacement of the initial memory location is made. If the initial memory location does not require replacement, a normal read operation occurs. If the initial memory location does require replacement, the entire location will be replaced by redundant memory.
After the determination of required replacement is made, the appropriate memory bits are read. The determination process may only begin after the location of the initial memory location is known. The initial memory location is known after complete address decoding. The time for complete address decoding and a determination of any replacement requirements means that dummy bytes may have to be inserted to an output stream of data for the device between the time the read instruction is received and the requested data can be output. In this way, the additional use of redundant memory may cause significant delays in receiving correct data.
For flash memories utilizing redundant memory bits, any increase in an amount of latency between the read command and data output is a significant impact to system efficiency. One desirable operation of flash memory would be to submit a continuous read operation command and have the data available in a normal amount of time regardless of whether redundant memory bits are incorporated or not.